CMOS imagers have been increasingly used as low cost imaging devices. A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells typically including a photodiode for integrating photo-generated charge in the underlying portion of a substrate, a source follower transistor which receives a voltage from the photodiode and provides an output signal, and a reset transistor for resetting the photodiode to a predetermined voltage before a charge integration period. In some implementations a transfer transistor may be used to transfer charge from the photodiode to a diffusion node connected to the source follower transistor.
FIG. 1 illustrates a known three-transistor (3T) pixel cell 20. As shown in FIG. 1, the photocollection region 30 of a photodiode is electrically connected to the gate of a source follower transistor 36, the output of which is selectively applied to column output line 41 by row select transistor 38. Reset transistor 32 selectively resets the photocollection region 30 to a predetermined voltage by coupling a voltage Vdd to the photocollection region 30 during a reset period which precedes or follows a charge integration period. A four-transistor (4T) design provides a transfer transistor to switch charge from the photocollection region 30 to the gate of source follower transistor 36.
While the 3T and 4T pixel cell structures work well, there is an ever increasing desire to minimize the number of transistors used in a pixel to reduce pixel size and increase pixel density in an array. There is also a further desire to simplify overall pixel design and fabrication complexity.